The present invention relates to a digital auto-phase-controlled retiming circuit for preventing retiming error as a retiming clock is automatically retiming input data in the center position of input data eye pattern.
To process data inputed from outside in all communication and/or digital processing systems, the retiming process with a reference clock without retiming error must be preceded above all.
At this time, the reference clock can be extracted from external input data or provided in the system itself and the phase relation between a retiming clock and input data is not invariable due to various factors such as circuit implementation, temperature and aging variations, etc.
As the digital auto-phase-controlled retiming circuit can be used in all communication and/or digital processing systems, the objective range of conventional technology which can be considered is very wide, but it is able to discuss on two following aspects.
First, it is the case of retiming input data with a clock extracted from input data in a digital data transmission repeater.
The received data are usually contaminated by signal attenuation through transmission channels, noise generated in transmission channels or receivers, and intersymbol interference due to insufficient transmission bandwidth, etc., thus clean waveforms must be recovered by retiming those data with the extracted clock.
For recovering a clock from input data, commonly used are a tuning circuit, a SAW filter and a PLL clock recovery circuit which are classified into self-timed clock extraction circuits.
In the tuning circuit or the SAW filter, the mutual phase difference between the extracted clock and the input data is greatly varied due to practical circuit implementation, temperature variation and the filter aging, etc., and accordingly, the phase of the retiming clock must be adjusted to the center of input data eye pattern using of a delay device which delays the input signal by a fixed amount. However, since it is so cumbersome that the mutual phase difference in every individual retiming circuit should be measured and adjusted. Moreover, the signal delay time is fixed, so that the retiming clock phase may be irrelevant against temperature, aging and supplied power level variation.
A circuit which is retiming by detecting the phase difference between the recovered clock and input data (here, input data phase means data transition moment with respect to clock phase and clock phase means the significant instant) and then shifting automatically the clock phase to the center of input data eye pattern, is utilize.
Those examples are as follows; `Automatic Timing Alignment for Regenerative Repeater published in Electronics Letters, Vol. 21, No. 24`, `An Unedersea Fiber-Optic Regenerator Using an Integrated Substrate Package and Flip-Chip SAW Mounting published in IEEE Jr. SAC, Vol. 2, No. 6`, `Novel Regenerator Having Simple Clock Extraction and Automatic Phase-Controlled Retiming Circuit published in Electronics Letters, Vol. 25, No. 1`.
However, a Gilbert cell or varacter diode, etc. being used at this time, which are component of an analog phase shifter, has a disadvantage for supplied power level changes.
Also, it is not easy to handle the phase shift control signals. In addition they are bulky in low frequency operation.
A timing recovery circuit, which utilizes a PLL clock recovery circuit, can be designed so that the significant instant of clock is retiming automatically in the center of input data eye pattern. One example is `Self-Correcting Clock Recovery Circuit with Improved Jitter Performance published in Electronics Letters, Vol. 23, No. 2`. But since utilizing an analog loop filter and voltage-controlled-oscillator this circuit has defects that are bigger in size and more complicated than the case of utilizing a SAW filter, etc.
Second, SONET (synchronous optical network), switching and subscriber systems are made up of many signal processing units and require data transmission between each unit.
At this time, because the reference clock is provided from the center clock supply station, it is not necessary to extract clocks from input data in each of signal processing units but to do retiming with provided clocks in the center of input data eye pattern.
As clocks and input data are transmitted to each unit through independent paths, it is difficult to know exactly their mutual phase relation between clock and data in each processing unit.
In a case of retiming by shifting the clock phase with the use of devices having fixed signal delay, there are defects which not only adjust and measure the phase difference between data and clocks against each of signal processing units, but also can be retiming in inappropriate position against temperature, supplied power level changes and aging variation.
As another example, there are also above problems in a case of applying data and clock into BER (bit error ratio) measuring equipments used always to test the performance of communication systems.
A conventional digital retiming circuit published in `Switching of 140 Mb/s Signal in Broadband Communication System in Electrical Communication Vol. 58, No. 4` has defects that it cannot be retiming in the center of input data eye pattern, and also a digital retiming circuit which consists of DPLL (digital PLL) has restriction in operation speed because an oscillator of higher frequency is necessary.